The invention relates to a method for switching a clock-controlled device having at least two operating statuses respectively controlled by an individual clock signal sequence. The operating statuses are selected by a static selection signal.
Electronic controls are successfully employed in a number of areas wherein a clock supplied from the outside in the form of a pulse sequence defines the chronological execution of the control function. Different operating statuses are frequently defined in such clock-controlled devices. These statuses can then also be respectively based on different clock signal sequences. It is conceivable that the clock signal sequences individually allocated to the operating statuses only differ from one another in terms of their phase relation, but have the same pulse repetition frequency. However, it can also occur that the events in the various operating statuses--prescribed by external boundary conditions--must sequence with differing speed, and that the individual clock signal sequences then even differ in terms of their pulse repetition frequency.
Without limitation thereto, let a practical application of such a clock-controlled unit be pointed out here by way of example. Peripheral devices of electronic data processing, particularly peripheral storage devices, are often connected to a data-processing system in groups, and are connected thereto via an allocated control unit. This unit assumes the job of monitoring the function of the peripheral storage devices that are connected, thereby initiating write/read events and transmitting the corresponding data from or to the data-processing system in a system-suited form. In accordance with known industrial standards for disk storage interfaces, for example, the data traffic between the control unit and an allocated disk storage device is synchronized in that various clock signal sequences are transmitted from the disk storage device to the control unit. When reading out stored data, for example, this can be a read clock signal, whereas a reference clock signal is employed for all other events, this reference clock signal being derived from read information which is stored on what is referred to as the servo surface of the disk storage device.
These clocks control a sequential controller in the control unit, whereby the problem results that a certain slip dependent on the respective phase relation of the participating clock signal sequences occurs in the transition from one operating status to another, i.e. when switching from one clock signal sequence to another. This fact is not yet critical per se. However, incomplete clock periods must be avoided, especially when the switchover--as frequently occurs--is initiated asynchronously relative to the clock signal sequence just selected. Otherwise, a faulty working of the sequential switching network in the control unit in which data loss or miscontrols can occur would result.
In such clock-controlled devices having a plurality of operating statuses respectively controlled by an individual clock signal sequence and which are in turn set by an externally supplied selection signal, it is therefore necessary to execute the clock switchover while taking chronological boundary conditions into consideration in order to assure an error-free transition from one operating status into another.